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rej03c0294-0003 rev.0.03 jul. 31, 2007 r1q2a3636/r1q2a3618/R1Q2A3609 36-mbit qdr?ii sram 2-word burst rej03c0294-0003 preliminary rev. 0.03 jul. 31, 2007 description the r 1 q2a3636 i s a 1,048,576-word by 36-bi t , t h e r 1 q2a3618 i s a 2,097,152-word by 18-bi t , and t h e r 1 q2a3609 i s a 4,194,304-word by 9-bi t sy nchronous quad dat a rat e st at i c r a m fabri cat ed wi t h advanced c m os t echnol ogy usi ng ful l c m os si x-t r ansi st or m e m o ry cel l . it i n t e grat es uni que sy nchronous peri pheral ci rcui t r y and a burst count er. al l input registers controlle d by an input clock pair (k and /k) and are latched on the positive edge of k and /k. these product s are sui t a bl e for appl i cat i ons whi c h requi re sy nc hronous operat i on, hi gh speed, l o w vol t a ge, hi gh densi t y and wi de bi t confi gurat i on. these product s are packaged i n 165-pi n pl ast i c fb ga package. features ? 1.8 v ?0.1 v power suppl y for core (v dd ) ? 1.4 v t o v dd power suppl y for i/ o (v ddq ) ? dll ci rcui t r y for wi de out put dat a va l i d wi ndow and fut u re frequency scal i ng ? separat e i ndependent read and wri t e dat a port s wi t h concurrent t r ansact i ons ? 100% bus utilization ddr r ead and write operation ? two-t i c k burst for l o w ddr t r ansact i on si ze ? two i nput cl ocks (k and / k ) for preci se ddr t i m i ng at cl ock ri si ng edges onl y ? two out put cl ocks (c and / c ) for preci se fl i ght t i m e and cl ock skew m a t c hi ng-cl ock and dat a del i v ered t oget h er t o receiving device ? in tern ally self-tim ed write co n t ro l ? clo c k - sto p cap ab ility with s restart ? user program m a bl e i m pedance out put ? fast cl ock cy cl e t i m e: 4.0 ns (250 m h z)/ 5 .0 ns (200 m h z)/ 6 .0 ns (167 m h z) ? si m p l e cont rol l ogi c for easy dept h expansi on ? jtag boundary scan not e s: qdr r a m s and quad dat a r a t e r a m s com p ri se a new fam i l y of product s devel oped by c y press sem i conduct o r, idt, nec , sam s ung, and r e nesas technol ogy c o rp. prel i m i n ary : the speci fi cat i ons of t h i s devi ce are subject t o change wi t hout not i ce. pl ease cont act y our nearest r e nesas technol ogy ' s sal e s dept . regardi ng speci fi cat i ons. page 1 of 23
r1q2a3636/r1q2a3618/R1Q2A3609 ordering information t y p e no . org a n i zatio n cy cle time clo ck freq u e n c y packag e no tes r1q2a3636abg-40r 4.0 ns 250 mhz r1q2a3636abg-50r 5.0 ns 200 mhz r1q2a3636abg-60r 1-m w o rd 36-bit 6.0 ns 167 mhz r1q2a3618abg-40r 4.0 ns 250 mhz r1q2a3618abg-50r 5.0 ns 200 mhz r1q2a3618abg-60r 2-m w o rd 18-bit 6.0 ns 167 mhz R1Q2A3609abg-40r 4.0 ns 250 mhz R1Q2A3609abg-50r 5.0 ns 200 mhz R1Q2A3609abg-60r 4-m w o rd 9-bit 6.0 ns 167 mhz plastic f b ga 165-pin plbg0165f b-a notes: 1. t y pe no. (0:1) r1 : renesas memory prefix (2:3) q2 : qdrii 2-w o rd burst sram q3 : qdrii 4-w o rd burst sram q4 : ddrii 2-w o rd burst sram q5 : ddrii 4-w o rd burst sram q6 : ddrii 2-w o rd burst sram separate i/o (4) a : v dd =1 .8 v (5:6) 36 : density = 36mb 72 : density = 72mb (7:8) 36 : organization = x36 18 : organization = x18 09 : organization = x9 pin arrangement r1q2a3636 series 1 2 3 4 5 6 7 8 9 1 0 1 1 a /cq v ss n c /w /bw2 /k /bw1 /r sa n c c q b q27 q18 d18 sa /bw3 k /bw0 sa d17 q 1 7 q 8 c d27 q28 d19 v ss sa sa sa v ss d16 q 7 d 8 d d28 d20 q19 v ss v ss v ss v ss v ss q16 d 1 5 d 7 e q29 d29 q20 v ddq v ss v ss v ss v ddq q15 d 6 q 6 f q30 q21 d21 v ddq v dd v ss v dd v ddq d14 q 1 4 q 5 g d30 d22 q22 v ddq v dd v ss v dd v ddq q13 d 1 3 d 5 h /doff v re f v ddq v ddq v dd v ss v dd v ddq v ddq v re f z q j d31 q31 d23 v ddq v dd v ss v dd v ddq d12 q 4 d 4 k q32 d32 q23 v ddq v dd v ss v dd v ddq q12 d 3 q 3 l q33 q24 d24 v ddq v ss v ss v ss v ddq d11 q 1 1 q 2 m d33 q34 d25 v ss v ss v ss v ss v ss d10 q 1 d 2 n d34 d26 q25 v ss sa sa sa v ss q10 d 9 d 1 p q35 d35 q26 sa sa c sa sa q9 d 0 q 0 r tdo tck sa sa sa /c sa sa sa t m s td i (top view) rej03c0294-0003 rev.0.03 jul. 31, 2007 page 2 of 23
r1q2a3636/r1q2a3618/R1Q2A3609 r1q2a3618 series 1 2 3 4 5 6 7 8 9 1 0 1 1 a /cq v ss sa /w /bw1 /k n c /r sa n c c q b n c q 9 d 9 sa n c k /bw0 sa n c n c q 8 c n c n c d 1 0 v ss sa sa sa v ss n c q 7 d 8 d n c d 1 1 q 1 0 v ss v ss v ss v ss v ss n c n c d 7 e n c n c q 1 1 v ddq v ss v ss v ss v ddq n c d 6 q 6 f n c q 1 2 d 1 2 v ddq v dd v ss v dd v ddq n c n c q 5 g n c d 1 3 q 1 3 v ddq v dd v ss v dd v ddq n c n c d 5 h / d o f f v re f v ddq v ddq v dd v ss v dd v ddq v ddq v re f z q j n c n c d 1 4 v ddq v dd v ss v dd v ddq n c q 4 d 4 k n c n c q 1 4 v ddq v dd v ss v dd v ddq n c d 3 q 3 l n c q 1 5 d 1 5 v ddq v ss v ss v ss v ddq n c n c q 2 m n c n c d 1 6 v ss v ss v ss v ss v ss n c q 1 d 2 n n c d 1 7 q 1 6 v ss sa sa sa v ss n c n c d 1 p n c n c q 1 7 sa sa c sa sa n c d 0 q 0 r t d o t c k s a sa sa /c sa sa s a t m s t d i (top view) R1Q2A3609 series 1 2 3 4 5 6 7 8 9 1 0 1 1 a /cq v ss sa /w nc /k n c /r sa s a c q b n c n c n c sa n c k /bw sa n c n c q 4 c n c n c n c v ss sa sa sa v ss n c n c d 4 d n c d 5 n c v ss v ss v ss v ss v ss n c n c n c e n c n c q 5 v ddq v ss v ss v ss v ddq n c d 3 q 3 f n c n c n c v ddq v dd v ss v dd v ddq n c n c n c g n c d 6 q 6 v ddq v dd v ss v dd v ddq n c n c n c h / d o f f v re f v ddq v ddq v dd v ss v dd v ddq v ddq v re f z q j n c n c n c v ddq v dd v ss v dd v ddq n c q 2 d 2 k n c n c n c v ddq v dd v ss v dd v ddq n c n c n c l n c q 7 d 7 v ddq v ss v ss v ss v ddq n c n c q 1 m n c n c n c v ss v ss v ss v ss v ss n c n c d 1 n n c d 8 n c v ss sa sa sa v ss n c n c n c p n c n c q 8 sa sa c sa sa n c d 0 q 0 r t d o t c k s a sa sa /c sa sa s a t m s t d i (top view) notes: 1. address expansion order for future higher density srams (i.e. 72mb 144mb 288mb): (9a 3a 10a) 2a 7a 5b. rej03c0294-0003 rev.0.03 jul. 31, 2007 page 3 of 23
r1q2a3636/r1q2a3618/R1Q2A3609 pin description n a m e i / o ty p e d e s c r i p t i o n s n o t e s s a i n p u t sy nchronous address inputs: t hese inputs ar e registered and must meet the setup and hold times around the rising edge of k for read cy cles and must meet the setup and hold times around the rising edge of /k fo r w r it e cy cles. all transactions operate on a burst-of-tw o w o rds (one clock period of bus activity ). t hese inputs are ignored w hen device is deselected. / r i n p u t sy nchronous read: w hen low , this input c auses the address inputs to be registered and a read cy cle to be initiated. t h is input must meet setup and hold times around the rising edge of k. /w i n p u t sy nchronous w r ite: w hen low , this input causes the address inputs to be registered and a w r it e cy cle to be initiated. t h is input must meet setup and hold times around the rising edge of k. /bw x i n p u t sy nchronous by te w r ites: w hen low , these i nputs cause their respective by te to be registered and w r itten during w r it e cy cles . t hese signals must meet setup and hold times around the rising edges of k and /k fo r each of the tw o rising edges comprising the w r it e cy cle. see by te w r ite t r uth t able for signal to data relationship. k, /k input input clock: t h is input clock pair regi sters address and control inputs on the rising edge of k, and registers data on the rising edge of k and the rising edge of /k. /k is ideally 180 degrees out of phase w i th k. a ll sy nchronous inputs must meet setup and hold times around the clock rising edges. t hese balls cannot remain v re f level. c, /c input output clock: t h is clock pair provides a user-controlled means of tuning device output data. t he rising edge of /c is used as the out put timing reference for first output data. t he rising edge of c is used as the output timing reference for second output data. ideally , /c is 180 degrees out of phase w i th c. c and /c may be tied high to force the use of k and /k as the output reference cl ocks instead of having to provide c and /c clocks. if tied high, c and /c must rema in high and not to be toggled during device operation. t hese balls cannot remain v re f level. /dof f i n p u t dll disable: w hen low , this input causes the dll to be by passed for /dof f input stable, low frequency operation. z q i n p u t output impedance matching input: t h is input is used to tune the device outputs to the sy stem data bus impedance. q and cq output impedance are set to 0.2 rq, w here rq is a resistor from this ball to ground. t h is ball can be connected directly to v ddq , w h ich enables the minimum impedance mode. t h is ball cannot be connected directly to v ss or left unconnected. tm s td i input ieee1149.1 test inputs: 1.8 v i/o levels. t hese balls may be left not t m s input connected if the jt ag function is not used in the circuit. t c k i n p u t ieee1149.1 clock input: 1.8 v i/o levels. t h is ball must be tied to v ss if the jt ag function is not used t c k input in the circuit. d 0 to d n i n p u t sy nchronous data inputs: input data must meet setup and hold times around the rising edges of k and /k during w r it e operations. s ee pin arrangement figures for ball site location of individual signals. t he 9 device uses d0 to d8. remaining signals are not used. t he 18 device uses d0 to d17. remaining signals are not used. t he 36 device uses d0 to d35. cq, /cq output sy nchronous echo clock outputs: t he edges of these outputs are tightly matched to the sy nchronous data outputs and can be used as a data valid indication. t hese signals run freely and do not stop w hen q tristates. t d o output ieee 1149.1 test output: 1.8 v i/o level. q 0 to q n o u t p u t sy nchronous data outputs: output data is sy nchronized to the respective c and /c, or to the respective k and /k if c and /c are tied high. t h is bus operates in response to /r commands. see pin arrangement figures for ball site location of individual signals. t he 9 device uses q0 to q8. remaining signals are not used. t he 18 device uses q0 to q17. re maining signals are not used. t he 36 device uses q0 to q35. rej03c0294-0003 rev.0.03 jul. 31, 2007 page 4 of 23
r1q2a3636/r1q2a3618/R1Q2A3609 n a m e i / o ty p e d e s c r i p t i o n s n o t e s v dd s u p p l y pow e r supply : 1.8 v nominal. see dc characteristics and operating v dd supply conditions for range. v ddq s u p p l y pow e r supply : isolated output buffer supply . no minally 1.5 v. 1.8 v is also permissible. see dc characteristics and oper ating conditions for range. v ss supply pow e r supply : ground. v re f hst l input reference voltage: nominally v ddq /2, but may be adjusted to improve sy stem noise margin. provides a refer ence voltage for the hst l input buffers. nc no connect: t hese signals are not interna lly connected. t hese signals can be left floating or connected to ground to improve package heat dissipation. notes: 1. all pow er supply and ground balls must be connected for proper oper ation of the device. block diagram (r1q2a3636 / r1q2a3618 / R1Q2A3609 series) address registry and logic data registry and logic memory array write register address /r /w k /k /w /bwx d (data in) /r k /k 72 /36 /18 output register 72 /36 /18 output select output buffer 19/20/21 36/18/9 36/18/9 q (data out) write driver sense amp 19/20/21 k cc , / c or k, /k zq 2 cq /cq mux 72 /36 /18 4/2/1 rej03c0294-0003 rev.0.03 jul. 31, 2007 page 5 of 23
r1q2a3636/r1q2a3618/R1Q2A3609 general description pow e r-up and initialization sequence the fol l o wi ng suppl y vol t a ge appl i cat i on sequence i s recom m e nded: v ss , v dd , v ddq , v ref th en v in . after the stable power, there are three possible sequences. 1. sequence when dll di sabl e (/ doff pi n fi xed l o w) just aft e r t h e st abl e power and cl ock (k, / k , c , / c ), 1024 nop cy cl es (m i n .) are requi red for al l operat i ons, i n cl udi ng jtag funct i ons, t o becom e norm a l . 2a. sequence cont rol l e d by / doff pi n when dll enabl e just aft e r t h e st abl e power and cl ock (k, / k , c , / c ), t a ke / doff t o be hi gh. the addi t i onal 1024 nop cy cl es (m i n .) are requi red t o l o ck t h e dll and for al l operat i ons t o becom e norm a l . 2b. sequence cont rol l e d by c l ock (/ doff pi n fi xed hi gh) when dll enabl e if / doff pi n i s fi xed hi gh wi t h unst a bl e cl ock, t h e cl ock (k, / k , c , / c ) m u st be st opped for 30ns (m i n .). duri ng st op cl ock st age, c pi n m u st t i e l o w for 30 ns (m i n .). c , / c , k and / k cannot rem a i n v ref lev e l. the addi t i onal 1024 nop cy cl es (m i n .) are requi red t o l o ck t h e dll and for al l operat i ons t o becom e norm a l . not e s: 1. aft e r k or c cl ock i s st opped, cl ock recovery cy cl es (1024 nop cy cl es (m i n .)) are requi red for read/ w ri t e operat i ons t o becom e norm a l . 2. w h en dll i s enabl e and t h e operat i ng frequency i s changed, dll reset shoul d be requi red agai n. aft e r dll reset agai n, t h e 1024 nop cy cl es (m i n .) are needed t o l o ck t h e dll. 1. sequence when dll disable (/doff pin fixed low) status power up unstable clock stage stable clock stage nop stage normal operation v dd c, /c, k, /k v ddq v ref v in 1024cycle min. 2a. sequence controlled by /doff pin when dll enable status power up unstable clock stage stable clock stage nop & dll locking stage normal operation v dd c, /c, k, /k 1024cycle min. v ddq v ref /doff rej03c0294-0003 rev.0.03 jul. 31, 2007 page 6 of 23
r1q2a3636/r1q2a3618/R1Q2A3609 2b. sequence controlled by clock (/do ff pin fixed high) when dll enable status power up unstable clock stage stop clock stage nop & dll locking stage normal operation v dd c, /c, k, /k 30ns min. 1024cycle min. v ddq v ref /doff dll constraints 1. dll uses either k or c clock as its synchronizing input, th e input should have low phase jitter which is specified as tkc var. 2. the l o wer end of t h e frequency at whi c h t h e dll can operat e i s 100m hz. programmable output impedance 1. out put buffer i m pedance can be program m e d by t e rm i n at i ng t h e zq bal l t o v ss t h rough a preci si on resi st or (r q). the val u e of r q i s fi ve t i m es t h e out put i m pedance desi red. the al l o wabl e range of r q t o guarant ee i m pedance m a t c hi ng wi t h a t o l e rance of 10% i s 250 ? typical. th e to tal ex tern al cap acitan ce o f zq b a ll m u st b e less th an 7 . 5 p f . rej03c0294-0003 rev.0.03 jul. 31, 2007 page 7 of 23
r1q2a3636/r1q2a3618/R1Q2A3609 k truth table operation k /r /w d or q data in input data d(a+ 0) d(a+ 1) write cy cle: load address, input w r ite data on consecutive k and /k rising edges l output clock k(t) / k ( t ) data out output data q(a+ 0) q(a+ 1) read cy cle: load address, output read data on consecutive c and /c rising edges l output clock /c(t+1) c ( t + 2 ) nop (no operation) h h d = or q = high-z standby (clock stopped) stopped p r e v i o u s s t a t e notes: 1. h: high level, l: low level, : don?t care, : rising edge. 2. data inputs are registered at k and /k rising edges. data outputs are delivered at c and /c rising edges, except if c and /c are hi gh, then data outputs are delivered at k and /k rising edges. 3. /r and /w must meet setup/hol d times around the rising edges (low to high) of k and are registered at the rising edge of k. 4. t h is device contains circuitry that w ill ensure the outputs w ill be in high-z during pow er-up. 5. refer to state diagram and ti ming diagrams for clarification. 6. when clocks are stopped, the follow i ng cases are recommended; the case of k = low , /k = high, c = low and /c = high, or the case of k = high, /k = low , c = high and /c = low . t h is condition is not essential, but permits most rapid restart by overcoming transmission line charging sy mmetrically . rej03c0294-0003 rev.0.03 jul. 31, 2007 page 8 of 23
r1q2a3636/r1q2a3618/R1Q2A3609 by te write truth table (x36) operation k / k / b w 0 /b w1 / b w 2 /bw3 write d0 to d35 ? l l l l ? l l l l write d0 to d8 ? l h h h ? l h h h write d9 to d17 ? h l h h ? h l h h w r ite d18 to d26 ? h h l h ? h h l h w r ite d27 to d35 ? h h h l ? h h h l w r ite nothing ? h h h h ? h h h h notes: 1. h: high level, l: low level, : rising edge. 2. assumes a w r it e cy cle w a s initiated. /bw x c an be altered for any portion of the burst w r it e operation provided that the setup and hold requirements are satisfied. by te write truth table (x18) operation k / k / b w 0 / b w 1 write d0 to d17 ? l l ? l l write d0 to d8 ? l h ? l h write d9 to d17 ? h l ? h l w r ite nothing ? h h ? h h notes: 1. h: high level, l: low level, : rising edge. 2. assumes a w r it e cy cle w a s initiated. /bw x c an be altered for any portion of the burst w r it e operation provided that the setup and hold requirements are satisfied. by te write truth table (x9) operation k / k / b w write d0 to d8 ? l ? l w r ite nothing ? h ? h notes: 1. h: high level, l: low level, : rising edge. 2. assumes a w r it e cy cle w a s initiated. /bw x c an be altered for any portion of the burst w r it e operation provided that the setup and hold requirements are satisfied. rej03c0294-0003 rev.0.03 jul. 31, 2007 page 9 of 23
r1q2a3636/r1q2a3618/R1Q2A3609 bus cy cle state diagram read port nop r init = 0 read double load new read address power up /r = h write port nop /w = h supply voltage provided supply voltage provided /r = l always /r = l /r = h write double at /k load new write address at /k /w = l always /w = l /w = h notes: 1. t he address is concatenated w i th one additional inte rnal lsb to facilitate burst operation. t he address order is alw a y s f i xed as : xxx? xxx+ 0, xxx? xxx+ 1. bus cy cle is terminated at the end of this sequence (burst count = 2). 2. read and w r ite state machines can be active simultaneously . 3. state machine control timi ng sequence is controlled by k. rej03c0294-0003 rev.0.03 jul. 31, 2007 page 10 of 23
r1q2a3636/r1q2a3618/R1Q2A3609 absolute maximum ratings p a r a m e t e r s y m b o l r a t i n g u n i t n o t e s input voltage on any ball v in ? 0.5 to v dd + 0.5 (2.5 v max.) v 1, 4 input/output voltage v i/o ? 0.5 to v ddq + 0.5 (2.5 v max.) v 1, 4 core supply voltage v dd ? 0.5 to 2.5 v 1, 4 output supply voltage v ddq ? 0.5 to v dd v 1 , 4 junction temperature t j + 125 (max) c storage temperature t st g ? 55 to + 125 c notes: 1. all voltage is referenced to v ss . 2. permanent device damage may occur if absolute maximum ratings are exceeded. f unctional operation should be restricted the o peration conditions. exposure to hi gher than recommended voltages for extended periods of time could affect device reliability . 3. t hese cmos memory circuits have been designed to m eet the dc and ac specificati ons show n in the tables after thermal equilibrium has been established. 4. t he follow i ng supply voltage app lication sequence is recommended: v ss , v dd , v ddq , v re f then v in . remember, according to the abso lute maximum ratings table, v ddq is not to exceed 2. 5 v, w hatever the instantaneous value of v ddq . recommended dc operating conditions (ta = 0 t o +70c ) pa ra me te r s y m b o l m i n ty p ma x u n i t note s pow e r supply voltage --core v dd 1 . 7 1 . 8 1 . 9 v pow e r supply voltage --i/o v ddq 1 . 4 1 . 5 v dd v input reference voltage --i/o v re f 0 . 6 8 0 . 7 5 0 . 9 5 v 1 input high voltage v ih ( dc) v re f + 0.1 ? v ddq + 0.3 v 2, 3 input low voltage v il ( dc) ? 0.3 ? v re f ? 0.1 v 2, 3 notes: 1. peak to peak ac component superimposed on v re f may not exceed 5% of v re f . 2. overshoot: v ih ( a c) v ddq + 0.5 v for t t kh kh /2 undershoot: v il ( a c) ? 0.5 v for t t kh kh /2 pow e r - u p : v ih v ddq + 0.3 v and v dd 1.7 v and v ddq 1.4 v for t 200 ms during normal operation, v ddq must not exceed v dd . control input signals may not have pulse w i dths less than t kh kl (min) or operate at cy cle rates less than t kh kh (min). during normal operation, v ih(dc) must not exceed v ddq and v il (dc) must not be low e r than v ss . 3. t hese are dc test criteria. t he ac v ih / v il levels are defined separately to measure timing parameters. dc characteristics (ta = 0 to +70 c, v dd = 1.8v 0.1v) ? 40 ? 50 ? 6 0 p a r a m e t e r sy mb o l m a x m a x m a x un i t no t e s ( 9 ) i dd 6 0 0 5 5 0 5 0 0 m a 1 , 2 , 3 ( 1 8 ) i dd 6 5 0 6 0 0 5 5 0 m a 1 , 2 , 3 operating supply current (read / writ e) ( 3 6 ) i dd 7 0 0 6 5 0 6 0 0 m a 1 , 2 , 3 standby supply current (nop) ( 9 / 18 / 36) i sb1 3 5 0 3 4 0 3 3 0 m a 2 , 4 , 5 rej03c0294-0003 rev.0.03 jul. 31, 2007 page 11 of 23
r1q2a3636/r1q2a3618/R1Q2A3609 pa ra me te r s y m b o l m i n ma x u n i t te s t c onditions note s input leakage current i li ? 2 2 a 1 0 output leakage current i lo ? 5 5 a 1 1 output high voltage v oh (low ) v ddq ? 0 . 2 v ddq v | i oh | 0.1 ma 8, 9 v oh v ddq /2 ? 0 . 0 8 v ddq /2 + 0 .08 v note 6 8, 9 output low voltage v ol (low ) v ss 0 . 2 v i ol 0.1 ma 8, 9 v ol v ddq /2 ? 0 . 0 8 v ddq /2 + 0 .08 v note 7 8, 9 notes: 1. all inputs (except z q, v re f ) are held at either v ih or v il . 2. i out = 0 ma. v dd = v dd max , t kh kh = t kh kh min. 3. operating supply currents are measured at 100% bus utilization. 4. all address / data inputs are static at either v in > v ih or v in < v il . 5. nop currents are valid w hen entering nop afte r all pending read and w r it e cy cles are completed. 6. outputs are im pedance-controlled. | i oh | = ( v ddq /2)/(rq/5) for values of 175 ? rq 350 ? . 7. outputs are im pedance-controlled. i ol = (v ddq /2)/(rq/5) for values of 175 ? rq 350 ? . 8. ac load current is higher than the show n dc values. ac i/o curves are available upon request. 9. hst l outputs meet jedec hst l class i standards. 10. 0 v in v ddq for all input balls (except v re f , zq, t c k, t m s, t d i ball). 1 1 . 0 v out v ddq (except t d o ball), output disabled. thermal resistance p a r a m e t e r s y m b o l ty p u n i t n o t e s junction to ambient ja 2 4 . 5 c / w junction to case jc 5 . 6 c / w note: t hese parameters are calculated under the condition of w i nd velocity = 1 m/s. capacitance (ta = +25c , f=1.0m hz, v dd = 1.8v, v ddq = 1.5v) pa ra me te r s y m b o l m i n ty p ma x u n i t te s t c onditions note s input capacitance c in ? 2 3 pf v in = 0 v 1, 2 clock input capacitance c cl k ? 2 3 pf v cl k = 0 v 1, 2 input/output capacitance (d, q, z q ) c i/o ? 3 4 . 5 pf v i/o = 0 v 1, 2 notes: 1. t hese parameters ar e sampled and not 100% tested. 2. ex cept jt ag (t ck, t m s, t d i, t d o) pins. ac test conditions (ta = 0 t o +70c , v dd = 1.8v 0.1v) input w a v e form (rise/fall time 1.25 v 0.25 v 0.75 v 0 .75 v test points rej03c0294-0003 rev.0.03 jul. 31, 2007 page 12 of 23
r1q2a3636/r1q2a3618/R1Q2A3609 output w a v e form v ddq /2 test points v ddq /2 output load condition 50 ? 0.75 v zq q v ref 250 ? z 0 = 50 ? sram v ddq /2 ac operating conditions pa ra me te r s y m b o l m i n ty p ma x u n i t note s input high voltage v ih ( a c) v re f + 0.2 ? ? v 1, 2, 3, 4 input low voltage v il ( a c) ? ? v re f ? 0.2 v 1, 2, 3, 4 notes: 1. all voltages referenced to v ss (gnd). 2. t hese conditions are for ac functions only , not for ac parameter test. 3. overshoot: v ih ( a c) v ddq + 0.5 v for t t kh kh /2 undershoot: v il ( a c) ? 0.5 v for t t kh kh /2 pow e r - u p : v ih v ddq + 0.3 v and v dd 1.7 v and v ddq 1.4 v for t 200 ms during normal operation, v ddq must not exceed v dd . control input signals may not have pulse w i dths less than t kh kl (min) or operate at cy cle rates less than t kh kh (min). 4. t o maintain a valid level, t he transitioning edge of the input must: a. sustain a constant slew rate from the current ac level through the target ac level, v il ( a c) or v ih ( a c) . b. reach at least the target ac level. c. after the ac target level is reached, cont inue to maintain at least the target dc level, v il ( dc) or v ih ( dc) . rej03c0294-0003 rev.0.03 jul. 31, 2007 page 13 of 23
r1q2a3636/r1q2a3618/R1Q2A3609 ac characteristics (ta = 0 to +70 c, v dd = 1.8v 0.1v) ? ? ? average clock cy cle time (k, /k, c, /c) t kh kh 4 . 0 0 5 . 2 5 5 . 0 0 6 . 3 0 6 . 0 0 8 . 0 0 n s clock phase jitter (k, /k, c, /c) t kc var ? 0 . 2 0 ? 0 . 2 0 ? 0 . 2 0 n s 3 clock high time (k, /k, c, /c) t kh kl 1 . 6 0 ? 2 . 0 0 ? 2 . 4 0 ? n s clock low time (k, /k, c, /c) t klkh 1 . 6 0 ? 2 . 0 0 ? 2 . 4 0 ? n s clock to /clock (k to /k, c to /c) t kh /kh 1 . 8 0 ? 2 . 2 0 ? 2 . 7 0 ? n s /clock to clock (/k to k, /c to c) t /khkh 1 . 8 0 ? 2 . 2 0 ? 2 . 7 0 ? n s clock to data clock (k to c, /k to /c) t k hch 0 1 . 1 0 0 1 . 6 0 0 2 . 1 0 n s dll lock time (k, c) t kc lock 1,024 ? 1 , 0 2 4 ? 1 , 0 2 4 ? c y c l e 2 k static to dll reset t kc reset 30 ? 3 0 ? 3 0 ? n s 7 c, /c high to output valid t chqv ? 0 . 4 5 ? 0 . 4 5 ? 0 . 5 0 n s c, /c high to output hold t chqx ? 0.45 ? ? 0.45 ? ? 0.50 ? n s c, /c high to echo clock valid t chcqv ? 0 . 4 5 ? 0 . 4 5 ? 0 . 5 0 n s c, /c high to echo clock hold t chcqx ? 0.45 ? ? 0.45 ? ? 0.50 ? n s cq, /cq high to output valid t cqhqv ? 0 . 3 0 ? 0 . 3 5 ? 0 . 4 0 n s 4 , 7 cq, /cq high to output hold t cqhqx ? 0.30 ? ? 0.35 ? ? 0.40 ? n s 4 , 7 c, /c high to output high-z t chqz ? 0 . 4 5 ? 0 . 4 5 ? 0 . 5 0 n s 5 c, /c high to output low - z t chqx1 ? 0.45 ? ? 0.45 ? ? 0.50 ? n s 5 address valid to k, /k rising edge t avkh 0 . 3 5 ? 0 . 4 0 ? 0 . 5 0 ? n s 1 control inputs valid to k rising edge t ivkh 0 . 3 5 ? 0 . 4 0 ? 0 . 5 0 ? n s 1 data-in valid to k, /k rising edge t d vkh 0 . 3 5 ? 0 . 4 0 ? 0 . 5 0 ? n s 1 k, /k rising edge to address hold t kh ax 0 . 3 5 ? 0 . 4 0 ? 0 . 5 0 ? n s 1 k, /k rising edge to control inputs hold t kh ix 0 . 3 5 ? 0 . 4 0 ? 0 . 5 0 ? n s 1 k, /k rising edge to data-in hold t k hdx 0 . 3 5 ? 0 . 4 0 ? 0 . 5 0 ? n s 1 notes: 1. t h is is a sy nchronous device. all addresses, data and control lines must meet the specified setup and hold times for all latching clock edges. 2. v dd slew rate must be less than 0.1 v dc per 50 ns fo r dll lock retention. dll lock time begins once v dd and input clock are stable. it is recommended that t he device is kept inactive during these cy cles. 3. clock phase jitter is the variance from clo ck rising edge to the next expected clock rising edge. 4. echo clock is very tightly controlled to data valid / dat a hold. by design, there is a 0.1 ns variation from echo clock to data. t he datasheet par ameters reflect tester guardbands and test setup variations. 5. t r ansitions are measured 100 mv from steady -state voltage. 6. at any given vo ltage and temperature t chqz is less than t chqx1 and t chqz less than t chqv . 7. t hese parameters are sampled. remarks: 1. t e st conditions as specified w i th the output loading as show n in ac t e st conditions unless otherw i se noted. 2. control input signals may not be operated w i th pulse w i dths less than t kh kl (min). 3. if c, /c are tied high, k, /k become t he references for c, /c timing parameters. 4. v ddq is +1.5 v dc. 5. control signals are /r, /w , /bw , /bw 0 , /bw 1 , /bw 2 and /bw 3 . bw n signals must operate at the same timing as data in. 6. t chqv , t chcqv are 0.65 ns and t chqx , t chcqx are -0.65 ns on r1q2a3636abg (-40r, -50r) devices. rej03c0294-0003 rev.0.03 jul. 31, 2007 page 14 of 23
r1q2a3636/r1q2a3618/R1Q2A3609 timing waveforms read and write timing 1 2 34 56 78 91 0 11 12 13 14 15 16 17 k q00 q01 q20 q21 q40 q41 q60 q61 tkhdx tdvkh tkhdx tdvkh /k /r /w address data in tchqv -tchqx tchqv -tchqx tcqhqv -tcqhqx -tchqx1 tchqz tchcqv -tchcqx tchcqv -tchcqx tkhkh tkhkl tklkh tkh/kh t/khkh tkhkh tkhkl tklkh tkh/kh t/khkh tkhch tkhch data out cq /cq c /c tkhax tavkh tkhix tivkh read write nop nop read write read write nop write read write nop nop nop nop tkhix tivkh a2 a1 a4 a3 a5 a7 a6 a8 d10 d11 d 30 d31 d 50 d51 d 70 d71 d 80 d81 a0 notes: 1. q00 refers to output from address a0+ 0 . q01 re fers to output from the next internal burst address follow i ng a0, i.e., a0+1. 2. outputs are disable (high- z ) one clock cy cle after a nop. 3. in this example, if address a0 = a1, then data q 00 = d10, q01 = d11. w r ite data is forw arded immediately as read results. 4. t o control read and w r ite oper ations, /bw signals must operate at the same timing as data in. rej03c0294-0003 rev.0.03 jul. 31, 2007 page 15 of 23
r1q2a3636/r1q2a3618/R1Q2A3609 jtag specification these products support a lim ited set of jtag functions as in ieee standard 1149.1. disabling the test access port it is possible to use this device without utilizing the tap. to disable the tap controller without interfering with norm a l operat i on of t h e devi ce, tc k m u st be t i e d t o v ss t o precl ude m i d l e vel i nput s. tdi and tm s are desi gned so an undriven input will produce a response identi cal to the application of a logic 1, and m a y be left unconnected. but they m a y also b e tied to v dd t h rough a 1k ? resi st or.tdo shoul d be l e ft unconnect ed. test access port (tap) pins sy mbol i/o pin assignments description notes tc k 2 r t e st clock input. all inputs are c aptured on the rising edge of t c k and all outputs propagate from t he falling edge of t c k. t m s 1 0 r t e st mode select. t h is is the comm and input for the t ap controller state machine. t d i 1 1 r t e st data input. t h is is the input side of the serial registers placed betw een t d i and t d o. t he register placed betw een t d i and t d o is determined by the state of the t ap cont roller state machine and t he instruction that is currently loaded in the t ap instruction. td o 1 r t e st data output. output changes in response to the falling edge of t c k. t h is is the output side of the seri al registers placed betw een t d i and t d o. notes: t he device does not have t r st (t ap reset). t he t e st -logic reset state is entered w h ile t m s is held high for five rising edges of t c k. t he t ap controlle r state is also reset on sram pow e r-up. tap dc operating characteristics (ta = 0 to +70 c, v dd = 1.8v 0.1v) pa ra me te r s y m b o l m i n ty p ma x u n i t note s input high voltage v ih + 1 .3 ? v dd + 0.3 v input low voltage v il ? 0.3 ? + 0 .5 v input leakage current i li ? 5.0 ? + 5 .0 a 0 v v in v dd output leakage current i lo ? 5.0 ? + 5 .0 a 0 v v in v dd , output disabled output low voltage v ol1 ? ? 0 . 2 v i olc = 100 a v ol2 ? ? 0 . 4 v i olt = 2 ma output high voltage v oh1 1 . 6 ? ? v | i ohc | = 100 a v oh2 1 . 4 ? ? v | i oht | = 2 m a notes: 1. all voltages referenced to v ss (gnd). 2. pow e r - u p : v ih v ddq + 0.3 v and v dd + 1 .7 v and v ddq +1.4 v for t 200 ms. 3. in ?ext est ? mode and ?sample? mode, v ddq is nominally 1.5 v. 4 . zq: v ih = v ddq . rej03c0294-0003 rev.0.03 jul. 31, 2007 page 16 of 23
r1q2a3636/r1q2a3618/R1Q2A3609 tap ac test conditions pa ra me te r s y m b o l conditions u n i t note s t e m p e r a t u r e t a 0 ta + 70 c input timing measurement reference levels v re f 0 . 9 v input pulse levels v il , v ih 0 to 1.8 v input rise/fall time tr, tf 1.0 ns output timing measurement re ference levels 0.9 v t e st load termination supply voltage (v tt ) 0 . 9 v output load see figures input w a v e form 1.8 v 0 v 0.9 v 0 .9 v test points output w a v e form 0.9 v test points 0.9 v output load condition external load at test 50 ? ? rej03c0294-0003 rev.0.03 jul. 31, 2007 page 17 of 23
r1q2a3636/r1q2a3618/R1Q2A3609 tap ac operating characteristics (ta = 0 t o +70c , v dd = 1.8v 0.1v) pa ra me te r s y m b o l m i n ty p ma x u n i t note s t e st clock (t ck) cy cle time t th th 1 0 0 ? ? n s t c k high pulse w i dth t th tl 4 0 ? ? n s t c k low pulse w i dth t tl th 4 0 ? ? n s t e st mode select (t ms) setup t mv t h 1 0 ? ? n s t m s hold t th m x 1 0 ? ? n s capture setup t cs 1 0 ? ? n s 1 capture hold t ch 1 0 ? ? n s 1 t d i valid to t c k high t dv t h 1 0 ? ? n s t c k high to t d i invalid t t hdx 1 0 ? ? n s t c k low to t d o unknow n t tl q x 0 ? ? n s t c k low to t d o valid t tl q v ? ? 2 0 n s notes: 1. t cs + t ch defines the minimum pause in ram i/o pad tr ansitions to assure pad data capture. tap controller timing diagram tck tdi tms tdo pi (sram) tthtl tthth ttlth tmvth tthmx tdvth tthdx tcs tch ttlqv ttlqx rej03c0294-0003 rev.0.03 jul. 31, 2007 page 18 of 23
r1q2a3636/r1q2a3618/R1Q2A3609 test access port registers re gis t e r na me le ngth sy mbol note s instruction register 3 bits ir [2:0] by pass register 1 bits bp id register 32 bits id [31:0] boundary scan register 109 bits bs [109:1] tap controller instruction set i r 2 i r 1 i r 0 in stru ctio n descrip tio n no t e s 0 0 0 ext est t he ext est instruction allow s ci rcuitry external to the component package to be tested. boundary scan regi ster cells at output balls are used to apply test vectors, w h ile those at input balls capture test results. t y pically , the first test vector to be applied using the ext est instruction w ill be shifted into the boundary sc an register using the preload instruction. t hus, during the updat e-ir state of ext est , the output driver is turned on and the preload data is driven onto the output balls. 1, 2, 3 0 0 1 i d c o d e t he idcode instruction causes t he id rom to be loaded into the id register w hen the controller is in capture-dr mode and places the id register betw een the t d i and t d o balls in shift-dr mode. t he idcode instruction is the default instructi on loaded in at pow er up and any time the controller is placed in the t e st-logic-reset state. 0 1 0 s a m p l e - z if the sample-z instruction is loaded in the instruction register, all ram outputs are forced to an inactive dr ive state (high-z ) , moving the t ap controller into the captur e-dr state loads the data in the rams input into the boundary scan register, and the boundar y scan register is connected betw een t d i and t d o w hen the t ap controller is moved to the shift-dr state. 3, 4 0 1 1 r e s e r v e d t he reserved instructions are not implemented but are reserved for future use. do not use these instructions. 1 0 0 sample (/preload) w hen the sample instruction is l oaded in the instruction register, moving the t ap controller into the c apture-dr state loads the data in the rams input and i/o buffers into t he boundary scan register. because the ram clock(s) are independent from the t ap clock (t ck) it is possible for the t ap to attempt to capture the i/o ring contents w h ile the input buffers are in transition (i.e., in a metastabl e state). although allow i ng the t ap to sample metastable input w ill not ha rm the device, repeatable results cannot be expected. moving the controller to shi ft-dr state then places the boundary scan register bet w een the t d i and t d o balls. 3 1 0 1 r e s e r v e d 1 1 0 r e s e r v e d 1 1 1 b y p a s s t he bypass instruction is loaded in t he instruction register w hen the by pass register is placed betw een t d i and t d o. t h is occurs w hen the t ap controller is moved to the shift- dr state. t h is allow s the board level scan path to be shortened to facilitate te sting of other devices in the scan path. notes: 1. data in output register is not guaranteed if ext est instruction is loaded. 2. after performing ext est , pow er-up conditions are r equired in order to return part to normal operation. 3. ram input signals must be stabilized for long enough to meet the t aps input data capture setup plus hold time (t cs plus t ch ). t he rams clock inputs need not be paused for any other t ap operati on except capturing the i/o ring contents into the boundary scan register. 4. clock recovery initialization cy cles are requi red to return from the sample-z instruction. rej03c0294-0003 rev.0.03 jul. 31, 2007 page 19 of 23
r1q2a3636/r1q2a3618/R1Q2A3609 boundary scan order signa l na me s signa l na me s bit # ball id x9 x18 x36 bit # ball id x9 x18 x36 1 6 r / c / c / c 5 0 8 b s a s a s a 2 6 p c c c 5 1 7 c s a s a s a 3 6 n s a s a s a 5 2 6 c s a s a s a 4 7 p s a s a s a 5 3 8 a / r / r / r 5 7 n s a s a s a 5 4 7 a n c n c / b w 1 7 r s a s a s a 5 5 7 b / b w / b w 0 / b w 0 7 8 r s a s a s a 5 6 6 b k k k 8 8 p s a s a s a 5 7 6 a / k / k / k 9 9 r s a s a s a 5 8 5 b n c n c / b w 3 1 0 1 1 p q 0 q 0 q 0 5 9 5 a n c /bw 1 /bw 2 1 1 1 0 p d 0 d 0 d 0 6 0 4 a /w /w /w 1 2 1 0 n n c n c d 9 6 1 5 c s a s a s a 1 3 9 p n c n c q 9 6 2 4 b s a s a s a 1 4 1 0 m n c q 1 q 1 6 3 3 a s a s a n c 1 5 1 1 n n c d 1 d 1 6 4 2 a v ss v ss v ss 1 6 9 m n c n c d 1 0 6 5 1 a / c q / c q / c q 1 7 9 n n c n c q 1 0 6 6 2 b n c q 9 q 1 8 1 8 1 1 l q 1 q 2 q 2 6 7 3 b n c d 9 d 1 8 1 9 1 1 m d 1 d 2 d 2 6 8 1 c n c n c d 2 7 2 0 9 l n c n c d 1 1 6 9 1 b n c n c q 2 7 2 1 1 0 l n c n c q 1 1 7 0 3 d n c q 1 0 q 1 9 2 2 1 1 k n c q 3 q 3 7 1 3 c n c d 1 0 d 1 9 2 3 1 0 k n c d 3 d 3 7 2 1 d n c n c d 2 8 2 4 9 j n c n c d 1 2 7 3 2 c n c n c q 2 8 2 5 9 k n c n c q 1 2 7 4 3 e q 5 q 1 1 q 2 0 2 6 1 0 j q 2 q 4 q 4 7 5 2 d d 5 d 1 1 d 2 0 2 7 1 1 j d 2 d 4 d 4 7 6 2 e n c n c d 2 9 2 8 1 1 h z q z q z q 7 7 1 e n c n c q 2 9 2 9 1 0 g n c n c d 1 3 7 8 2f n c q 1 2 q 2 1 3 0 9 g n c n c q 1 3 7 9 3f n c d 1 2 d 2 1 3 1 1 1 f n c q 5 q 5 8 0 1 g n c n c d 3 0 3 2 1 1 g n c d 5 d 5 8 1 1f n c n c q 3 0 3 3 9 f n c n c d 1 4 8 2 3 g q 6 q 1 3 q 2 2 3 4 1 0 f n c n c q 1 4 8 3 2 g d 6 d 1 3 d 2 2 3 5 1 1 e q 3 q 6 q 6 8 4 1 h / d o f f / d o f f / d o f f 3 6 1 0 e d 3 d 6 d 6 8 5 1 j n c n c d 3 1 3 7 1 0 d n c n c d 1 5 8 6 2 j n c n c q 3 1 3 8 9 e n c n c q 1 5 8 7 3 k n c q 1 4 q 2 3 3 9 1 0 c n c q 7 q 7 8 8 3 j n c d 1 4 d 2 3 4 0 1 1 d n c d 7 d 7 8 9 2 k n c n c d 3 2 4 1 9 c n c n c d 1 6 9 0 1 k n c n c q 3 2 4 2 9 d n c n c q 1 6 9 1 2 l q 7 q 1 5 q 2 4 4 3 1 1 b q 4 q 8 q 8 9 2 3 l d 7 d 1 5 d 2 4 4 4 1 1 c d 4 d 8 d 8 9 3 1 m n c n c d 3 3 4 5 9 b n c n c d 1 7 9 4 1 l n c n c q 3 3 4 6 1 0 b n c n c q 1 7 9 5 3 n n c q 1 6 q 2 5 4 7 1 1 a c q c q c q 9 6 3 m n c d 1 6 d 2 5 4 8 1 0 a s a n c n c 9 7 1 n n c n c d 3 4 4 9 9 a s a s a s a 9 8 2 m n c n c q 3 4 6 rej03c0294-0003 rev.0.03 jul. 31, 2007 page 20 of 23
r1q2a3636/r1q2a3618/R1Q2A3609 signa l na me s signa l na me s bit # ball id x9 x18 x36 bit # ball id x9 x18 x36 9 9 3 p q 8 q 1 7 q 2 6 1 0 5 4 p s a s a s a 1 0 0 2 n d 8 d 1 7 d 2 6 1 0 6 5 p s a s a s a 1 0 1 2 p n c n c d 3 5 1 0 7 5 n s a s a s a 1 0 2 1 p n c n c q 3 5 1 0 8 5 r s a s a s a 1 0 3 3 r s a s a s a 1 0 9 ? i n t e r n a l int e r n a l int e r n a l 1 0 4 4 r s a s a s a notes: in boundary scan mode, 1. clock balls (k, /k, c, /c) are referenced to each other and must be at opposite logic levels for reliable operation. 2. cq and /cq data are sy nchronized to the re spective c and /c (except ext est , sample-z ) . 3. if c and /c tied high, cq is generated w i th respect to k and /cq is generated w i th respect to /k (except ex t est , sample-z). 4. z q must be driven to v ddq supply to ensure consistent results. rej03c0294-0003 rev.0.03 jul. 31, 2007 page 21 of 23
r1q2a3636/r1q2a3618/R1Q2A3609 id register part re v i s i on numbe r (31:29) ty pe numbe r (28:12) ve ndor j e dec c ode (11:1) start bit (0) ? ? 0 0mmm 0ww0 10q0 b0s0 ? ? r1q2a3636 000 0 0010 0110 1010 0010 0100 0100 011 1 r1q2a3618 000 0 0010 0100 1010 0010 0100 0100 011 1 R1Q2A3609 000 0 0010 0000 1010 0010 0100 0100 011 1 notes: 1. t y pe number mmm :density 011:72m b, 010:36mb, 001:18mb w w :organization 11: x 36, 10: x 18, 00: x 9, 01: x 8 q :qdr/ddr 1: qdr, 0: ddr b :burst lengths 1: 4-w o rd burst, 0: 2-w o rd burst s :i/o 1: separate i/o, 0: common i/o tap controller state diagram select ir scan capture ir shift ir exit1 ir pause ir exit2 ir update ir 0 0 1 0 1 1 0 1 0 0 1 select dr scan capture dr shift dr exit1 dr pause dr exit2 dr update dr 0 0 1 0 1 1 0 1 0 0 1 run test/idle 0 10 1 test logic reset 1 1 0 0 11 notes: the value adjacent to each state transition in this figure represents the signal present at tms at the time of a rising edge at tck. no matter what the original state of the contro ller, it will enter test-logic-reset when tms is held high for at least five rising edges of tck. rej03c0294-0003 rev.0.03 jul. 31, 2007 page 22 of 23
r1q2a3636/r1q2a3618/R1Q2A3609 rej03c0294-0003 rev.0.03 jul. 31, 2007 page 23 of 23 package dimensions r 1 q2a3636/ r 1 q2a3618/ r 1 q2a3609 (plb g0165fb - a) 1 y s ys s b a a 1 1 23456789 1 0 1 1 b c d e f g h j k l m n p r index a a plbg0165fb-a p-lbga165-15x17-1.00 d e s d s e z d z e mass[typ.] 0.7g bp-165a renesas code jeita package code previous code 0.25 y 1 w v 0.20 17.00 1.46 0.37 0.32 0.27 0.55 0.50 0.45 1.00 0.15 15.00 y x b a reference symbol dimension in millimeters min nom max a 1 e 17.10 15.10 14.90 16.90 1.34 1.40 sab s e e 0.07 b m m d e
revision history r1q2a3636/r1q2a3618/R1Q2A3609 data sheet contents of modification rev. date page description 0.01 sep. 25, 2006 ? initial issue 0.02 feb. 22, 2007 23 package dimensions plbg0165fc-a to plbg0165fb-a 0.03 jul. 31, 2007 6 11 12 14 general description: adding descrip tion for clock stop to reset dll. dc characteristics: fixing data sheet errata for standby supply current (nop) since the previous value were same as 1st generation devices. i sb1 (-40r/-50r/-60r) (max): 350/340/330 ma capacitance: reducing c apacitance value to describe actual performance. c in (typ/max): 2/3 pf c clk (typ/max): 2/3 pf c i/o (typ/max): 3/4.5 pf ac characteristics: average clock cycle time is enlarged. t khkh (-60r) (max): 8.00 ns clock to data clock is tightened to reduce switching noise between outputs switching while inputs are being sampled. t khch (-40r/-50r/-60r) (max) : 1.10/1.60/2.10 ns adding of remarks 6 for t chqv , t chcqv , t chqx , and t chcqx on r1q2a3636abg (-40r, -50r) devices.
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any of the foregoing applications shall indemnify and hold harmless renesas technology corp., its affiliated companies and their officers, dir ectors, and employees against any and all damages arising out of such applications. 9. you should use the products described herein within the range specified by renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas sha ll have no liability for malfunctions or damages arising out of the use of renesas products beyond such specified ranges. 10. although renesas endeavors to improve the quality and reliability of its products, ic products have specific characteristic s such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. please be sure to implement safety measures to guard against the poss ibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas product, such as safety design for hardware and software includin g but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. among others, sinc e the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. in case renesas products listed in this document are detached from the products to which the renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. you should implement safety measures so that renesas products may not be easily detached from your products. renesas shall have no liability for damages arising out of such detachment. 12. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from r enesas. 13. please contact a renesas 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